1. Field of the Invention
The present invention relates to a data transfer technique and, more particularly, to a data transmission apparatus for transferring data to an output device for outputting (for example, printing or displaying) digital image data.
2. Description of the Related Art
In recent years, the resolution of an image output from a digital image processing apparatus has become higher, and the data rate has increased. Since a last output unit always needs to output image data at a given interval, it requires a buffer memory.
On the other hand, in recent years, a high speed connection standard has been defined for inter-chip connection. Japanese Patent Laid-Open No. 2006-201909 (patent literature 1), for example, has proposed a data transfer method using PCI Express as a high speed connection standard.
In PCI Express, a plurality of link states, that is, L0, L0s, L1, and L2 are defined to reduce power consumption. An overview of the link states is described in, for example, “PCI Express System Architecture” (ISBN: 0-321-15630-7) (Addison-Wesley, 2003), pp. 567-645. The L0 state indicates a normal state, and the L0s to L2 states indicate a power saving state. The power consumption lowers in the order from L0s to L2. Patent literature 1 disclosed a technique of setting each packet interval in a series of transfer operations started with line synchronization to be equal to or shorter than a transition time to the power saving state L0s, which has been defined in the PCI Express standard, in a system for transferring image data in synchronism with a line synchronization signal or frame synchronization signal. This suppresses unnecessary transition to L0 during a series of data transfer operations, and improves the power saving effect by prolonging the total time of the power saving state (L0s).
Since the method described in patent literature 1 uses the L0s state, in which the power saving effect is relatively low, of the power saving states defined in the PCI Express standard, it cannot be expected to significantly improve the power saving effect. Furthermore, since power saving transition defined in the PCI Express standard is based on a period of time during which a state (=a logically idle state) wherein data transfer is not performed is maintained, a relatively long time is required to transit to a power saving state after data transfer is completed.
The present invention provides a technique of causing a data transmission apparatus to efficiently transit, while data transfer is not performed, to a state in which the power saving effect is higher.